DOCUMENT NO. REV.NO PAGE
STANDARD
NAME
00 5/20
4.8.4 M68 type CPU bus write in timing
Fig-4 Data write-in Timing Diagram(M68 bus interface)
4.8.5 M68 type CPU bus read-out Timing
Fig-5 Data read-out Timing Diagram (M68)
4.9 Connector Pin Assignment
Fifteen of though hole are prepared for power supply
And signal interface. A connecter may be able to soldered
to the holes. Location and dimensions are Shown at fig-8
on page 7/20.
！) The third hole (pin #3) can be used for reset input if the
soldering pad “jp1” is short-circuited.
(Refer to “Fig_6 System Block Diagram” on next )
No Signal No
SIGNAL
1 GND 8 DB1
2Vcc9DB2
3 */RST 10 DB3
4RS11DB4
5
R/W(/WR)
12 DB5
6 E(/RD) 13 DB6
7DB014DB7
T1Y
TU
G
FD2/FD9
Vuj*tu.t1y+
Okp"42pu
Vyn*G+
Okp"452pu
VJ
Okp"32pu
Vyj
Okp"452pu
Ve{e
Okp":2pu
XCNKF
Vuw*fcvc+
Okp":2pu
VJYT*FCVC+
Okp"32pu
Tsh(rs,r/w)Th
Min 20nsMin 10ns
Vyn*G+
Okp"452pu
Twh
Min 230ns
Tdly
Max 160ns
Thrd
Min 5ns
Tcyc
Max 160ns
R/W
RS
E
DB0-DB7
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